Hyderabad, Jan. 30 Electronic design automation (EDA) provider Cadence Design Systems has developed a design solution for low power chips.

This solution from the $1.3 billion EDA tool provider integrates design, verification and implementation of low power chips, thereby automating the entire process and compressing development time.

The Group Marketing Director, Digital IC., Cadence, Mr Mohit Bhatnagar, said the semiconductor industry is focussed on cutting down power consumption of chips and this design solution brings in the advantage of working on power right from the early chip design stage, and thereby eliminates a lot of manual work.

Speaking to Business Line, Mr Bhatnagar said that the company had developed what they claimed was the industry's first solution for the design, verification and implementation of low power system on chip (SoC) that allows designers to work right from the architecture stage.

Mr Bhatnagar said that India is emerging as a system design centre for both specialised SoC companies but also some of the large outsourcing service providers such as Wipro that partner semiconductor companies helping them in design work. This will improve productivity through integration and automation and also reduce risk of logic errors, he explained.

Significantly, this solution also features a simulator that complements the design and automation process.

Explaining the significance of this new design solution, Mr Bhatnagar said that the low power design techniques are moving to the mainstream as demand for power saving devices and gadgets increase.

Most of the portable devices need enhanced battery life.

This calls for design optimisation with better heat management.